In a computer system, various events are detected by the hardware and must be subsequently handled by a processor. These events include signals received on inbound Input/Output (I/O) interfaces, power and cooling systems alerts, error conditions, and failure conditions. Sometimes these events can happen faster than they can be handled in real time by the processor. To overcome this, a small memory element is typically added to the system to temporarily store the events until they can be handled by the processor. The memory element is often structured as a first-in, first-out (FIFO) buffer in a communication system.
When the processor is physically and logically located at a distance from the FIFO, each access that the processor makes to read the FIFO takes a considerable amount of time. As processors get faster, the number of processor cycles consumed waiting for the returned FIFO data increases. As this problem has been recognized, other related problems have been experience during development. When the FIFO fills with many events, the processor must access the FIFO for each event in the FIFO. Each time an event is put into the FIFO, the system causes an interrupt to the processor. These events cause considerable overhead to the processor since the processor typically makes a context switch to software used to handle the interrupt.